1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device.
This application claims the benefit of Korean Patent Application No. 10-2006-0085454, filed on Sep. 6, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of Related Art
Generally, flash memory devices have three main operating modes, i.e., a program mode, an erase mode, and a read mode. The cycle of an internal clock signal, which is required in an internal circuit of a flash memory device, is different according to an operating mode. Conventional flash memory devices include separate oscillation circuits for the respective operating modes in order to generate internal clock signals having different cycles according to the operating modes.
Meanwhile, flash memory devices need high voltage to erase and program data and thus include a high-voltage generator therewithin to generate the high voltage. The high-voltage generator includes a plurality of charge pumps connected in series. Each charge pump generates high voltage by performing pumping in response to an oscillation signal. This oscillation signal is also generated by an internal oscillation circuit included within a flash memory device.
FIG. 1 is a schematic block diagram of a conventional oscillation circuit 20. Referring to FIG. 1, the conventional oscillation circuit 20 includes separate oscillators (or OSC) 21, 22, and 23 for the read mode, the program (or PGM) mode, and the erase (or ERS) mode, respectively. The conventional oscillation circuit 20 also includes a switching circuit 24 to select one of oscillation signals CLK1, CLK2, and CLK3 respectively output from the oscillators 21, 22, and 23 and to provide an internal oscillation signal LCLK.
FIG. 2 is a circuit diagram of the oscillator 21 illustrated in FIG. 1. Referring to FIG. 2, the conventional oscillator 21 includes a reference voltage generator 310, a first comparison signal generator 320, and a second comparison signal generator 330, and a latch 340.
The reference voltage generator 310 includes a PMOS transistor P1 controlled by an enable signal EN, first and second resistors R1 and R2, and an NMOS transistor to generate a reference voltage Vref having a predetermined voltage level.
The first comparison signal generator 320 includes a detector and a comparator 321. The detector includes a PMOS transistor P2, two NMOS transistors N2 and N3, and a capacitor C1, which are sequentially connected in series between a power supply voltage VDD and a ground voltage VSS. The PMOS transistor P2 and the NMOS transistor N2 are turned on or off by a feedback signal S1 and the NMOS transistor N3 is turned on or off by the reference voltage Vref. The comparator 321 compares the reference voltage Vref with a detection signal V1 and outputs a comparison signal V3 corresponding to a result of the comparison.
The second comparison signal generator 330 has the same structure as the first comparison signal generator 320 and compares the reference voltage Vref with a detection signal V2 so as to output a comparison signal V4 as a result of the comparison.
The latch 340 includes two NAND gates 341 and 342 to generate first and second feedback signals S1 and S2. The second feedback signal S2 is output as an oscillation signal CLK1.
In conventional flash memory devices, an oscillation circuit includes the oscillator having the structure illustrated in FIG. 2 for each of the read, program, and erase modes. The cycle of an internal clock signal is adjusted in each mode by selecting one of oscillation signals output from the oscillators corresponding to the respective modes. Although it is possible to adjust the cycle according to an operating mode, oscillators need to be switched when the operating mode is changed At the moment of switching of two oscillators, the cycle of the internal clock signal may unexpectedly change or a glitch may occur.